In the computing industry, it is quite common to transfer data and commands between a plurality of data processing devices, such as for example, computers, printers, memories and the like, across a system or data bus. The usual bus architecture includes both a parallel and serial bus which interconnects data processing units and peripheral devices to permit the exchange of data and messages at high speed.
The typical system or data bus is defined by the hardware characteristics under which it operates. These hardware requirements are generally referred to as the bus protocol. The protocols influence both the mode and manner of data transfer on the bus. The protocol is usually dictated by the microprocessor attached to the bus. Thus, all data processing devices coupled to the bus are designed to utilize the bus protocol of the microprocessor in the computer system. For example, all data transfers in a computer system utilizing Motorola's 68030 or 68040 microprocessor occur using the bus protocol of the 68030 or 68040 respectively.
Some bus protocols accommodate data transfering devices which utilize distinct internal databuses of a variety of sizes. In this case, the processor in the computer system normal controls and directs the data being transfered to specific lines in the data bus such that the particular device sending or receive data can operate.
Problems arise where data transfering devices designed to operate under one such protocol are needed or desired in a computer system operating with a different protocol. For instance, where certain application specific computer chips are designed to operate in a 68030-based computer system, the chips could not be used in a 68040-based system. The 68040 bus is quite different than the bus defined for the 68030. Differences between the two buses involve the manner in which data is transfered in both size and byte alignment. For example, the 68040-based computer system requires transfers to be one, two or four bytes using specific address offsets, while a 68030-based computer system is capable of transfers of one, two, three or four bytes at any address offset. Furthermore, differences in the clock speeds at which the buses operate also prevent devices designed for use in one system to be used in another. These differences in protocols prevent data transferring devices of different protocols from being used together.
The present invention provides a data path apparatus which allows data transfers between devices on one bus utilizing one protocol and devices on another bus in the computer system employing a different protocol. The bus adapter of the present invention couples two buses operating at different speeds and aligns data to accommodate devices of a varying data specifications. Thus, the data path apparatus of the present invention directs the data in a specific temporal order and on specific parts of the system data bus to allow devices using different protocols and having different internal databuses to transfer data between themselves.